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ltc2208-14 1 220814fb 14-bit, 130msps adc the ltc ? 2208-14 is a 130msps, sampling 14-bit a/d converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 700mhz. the input range of the adc can be optimized with the pga front end. the ltc2208-14 is perfect for demanding communications applications, with ac performance that includes 77.1dbfs noise floor and 98db spurious free dynamic range (sfdr). ultralow jitter of 70fs rms allows undersampling of high input frequencies with excellent noise performance. maximum dc specs include 1.5lsb inl, 0.5lsb dnl (no missing codes). the digital output can be either differential lvds or single-ended cmos. there are two format options for the cmos outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. a separate output power supply allows the cmos output swing to range from 0.5v to 3.6v. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl or cmos inputs. an optional clock duty cycle stabilizer al- lows high performance at full speed with a wide range of clock duty cycles. n telecommunications n receivers n cellular base stations n spectrum analysis n imaging systems n ate n sample rate: 130msps n 77.1dbfs noise floor n 98db sfdr n sfdr >81db at 250mhz (1.5v p-p input range) n pga front end (2.25v p-p or 1.5v p-p input range) n 700mhz full power bandwidth s/h n optional internal dither n optional data output randomizer n lvds or cmos outputs n single 3.3v supply n power dissipation: 1.32w n clock duty cycle stabilizer n pin compatible 16-bit version 130msps: ltc2208 (16-bit) n 64-pin (9mm 9mm) qfn package 32k point fft, f in = 15.11mhz, C1db, pga = 0, rand on, dither off C + s/h amp correction logic and shift register output drivers 14-bit pipelined adc core internal adc reference generator 1.25v common mode bias voltage clock/duty cycle control d13 ? ? ? d0 pga shdn dith mode lvds rand v cm analog input 220814 ta01 cmos or lvds 0.5v to 3.6v 3.3v 3.3v sense ognd ov dd 2.2f 0.1f 0.1f 0.1f 0.1f v dd gnd adc control inputs ain + enc + ain C enc C of clkout frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g05 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 typical application description features applications l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc2208-14 2 220814fb supply voltage (v dd ) ................................... C 0.3v to 4v digital output ground voltage (ognd) ........ C 0.3v to 1v analog input voltage (note 3) ..... C 0.3v to (v dd + 0.3v) digital input voltage .................... C 0.3v to (v dd + 0.3v) digital output voltage ................ C 0.3v to (ov dd + 0.3v) power dissipation ............................................ 2000mw operating temperature range ltc2208c-14 ........................................... 0c to 70c ltc2208i-14 ........................................C40c to 85c storage temperature range ..................C 65c to 150c digital output supply voltage (ov dd ) .......... C 0.3v to 4v ov dd = v dd (notes 1 and 2) pin configuration absolute maximum ratings order information lead free finish tape and reel part marking* package description temperature range ltc2208cup-14#pbf ltc2208cup-14#trpbf ltc2208up-14 64-lead (9mm 9mm) plastic plastic qfn 0c to 70c ltc2208iup-14#pbf ltc2208iup-14#trpbf ltc2208up-14 64-lead (9mm 9mm) plastic plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ converter characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) parameter conditions min typ max units integral linearity error differential analog input (note 5) l 1 1.5 lsb differential linearity error differential analog input l 0.2 0.5 lsb offset error (note 6) l 2 10.8 mv offset drift 10 v/ c gain error external reference l 0.2 2.3 %fs full-scale drift internal reference external reference 30 15 ppm/c ppm/c transition noise external reference 0.8 lsb rms top view 65 up package 64-lead (9mm s 9mm) plastic qfn sense 1 gnd 2 v cm 3 gnd 4 v dd 5 v dd 6 gnd 7 a in + 8 a in C 9 gnd 10 gnd 11 enc + 12 enc C 13 gnd 14 v dd 15 v dd 16 48 d9 + /da4 47 d9 C /da3 46 d8 + /da2 45 d8 C /da1 44 d7 + /da0 43 d7 C /dnc 42 d6 + /dnc 41 d6 C /clkouta 40 clkout + /clkoutb 39 clkout C /ofb 38 d5 + /db13 37 d5 _ /db12 36 d4 + /db11 35 d4 C /db10 34 d3 + /db9 33 d3 C /db8 64 pga 63 rand 62 mode 61 lvds 60 of + /0fa 59 of C /da13 58 d13 + /da12 57 d13 C /da11 56 d12 + /da10 55 d12 C /da9 54 d11 + /da8 53 d11 C /da7 52 d10 + /da6 51 d10 C /da5 50 ognd 49 ov dd v dd 17 gnd 18 shdn 19 dith 20 nc 21 nc 22 dnc/db0 23 dnc/db1 24 d0 C /db2 25 d0 + /db3 26 d1 C /db4 27 d1 + /db5 28 d2 C /db6 29 d2 + /db7 30 ognd 31 ov dd 32 exposed pad (pin 65) is gnd, must be soldered to pcb board t jmax = 150c, ja = 20c/w
ltc2208-14 3 220814fb the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) analog input symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 3.135v v dd 3.465v 1.5 to 2.25 v p-p v in, cm analog input common mode differential input (note 7) l 1 1.25 1.5 v i in analog input leakage current 0v a in + , a in C v dd l C1 1 a i sense sense input leakage current 0v sense v dd l C3 3 a i mode mode pin pull-down current to gnd 10 a i lv d s lvds pin pull-down current to gnd 10 a c in analog input capacitance sample mode enc + < enc C hold mode enc + > enc C 6.5 1.8 pf pf t ap sample-and-hold acquisition delay time 1ns t jitter sample-and-hold acquisition delay time jitter 70 fs rms cmrr analog input common mode rejection ratio 1v < (a in + = a in C ) <1.5v 80 db bw-3db full power bandwidth r s 25 700 mhz the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C 1dbfs. (note 4) symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 77.1 74.9 dbfs dbfs 30mhz input (2.25v range, pga = 0), t a = 25oc 30mhz input (2.25v range, pga = 0) 30mhz input (1.5v range, pga = 1) l 75.7 75.4 77 77 74.9 dbfs dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 76.9 74.8 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1), t a = 25oc 140mhz input (1.5v range, pga = 1) l 73.5 73.3 76.4 74.6 74.6 dbfs dbfs dbfs 250mhz input (2.25v range, pga = 0) 250mhz input (1.5v range, pga = 1) 75 73.6 dbfs dbfs sfdr spurious free dynamic range 2 nd or 3 rd harmonic 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 98 98 dbc dbc 30mhz input (2.25v range, pga = 0) 30mhz input (1.5v range, pga = 1) l 84 96 98 dbc dbc 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 90 93 dbc dbc 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) l 81.5 85 95 dbc dbc 250mhz input (2.25v range, pga = 0) 250mhz input (1.5v range, pga = 1) 76 81 dbc dbc dynamic accuracy
ltc2208-14 4 220814fb symbol parameter conditions min typ max units sfdr spurious free dynamic range 4 th harmonic or higher 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 100 100 dbc dbc 30mhz input (2.25v range, pga = 0) 30mhz input (1.5v range, pga = 1) l 87 100 100 dbc dbc 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 100 100 dbc dbc 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) l 85 95 95 dbc dbc 250mhz input (2.25v range, pga = 0) 250mhz input (1.5v range, pga = 1) 90 90 dbc dbc s/(n+d) signal-to-noise plus distortion ratio 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 77 74.8 dbfs dbfs 30mhz input (2.25v range, pga = 0), t a = 25oc 30mhz input (2.25v range, pga = 0 30mhz input (1.5v range, pga = 1) l 75.4 75.1 76.9 76.9 74.7 dbfs dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 76.6 74.6 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1), t a = 25oc 140mhz input (1.5v range, pga = 1) l 73.4 73 76.3 74.5 74.5 dbfs dbfs dbfs 250mhz input (2.25v range, pga = 0) 250mhz input (1.5v range, pga = 1) 73.6 72.9 dbfs dbfs sfdr spurious free dynamic range at C25dbfs dither off 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 105 105 dbfs dbfs 30mhz input (2.25v range, pga = 0) 30mhz input (1.5v range, pga = 1) 105 105 dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 105 105 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 100 100 dbfs dbfs 250mhz input (2.25v range, pga = 0) 250mhz input (1.5v range, pga = 1) 100 100 dbfs dbfs sfdr spurious free dynamic range at C25dbfs dither on 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 115 115 dbfs dbfs 30mhz input (2.25v range, pga = 0) 30mhz input (1.5v range, pga = 1) l 95 110 110 dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 110 110 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 107 107 dbfs dbfs 250mhz input (2.25v range, pga = 0) 250mhz input (1.5v range, pga = 1) 105 105 dbfs dbfs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C 1dbfs. (note 4) dynamic accuracy
ltc2208-14 5 220814fb the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) common mode bias characteristics parameter conditions min typ max units v cm output voltage i out = 0 1.15 1.25 1.35 v v cm output tempco i out = 0 40 ppm/c v cm line regulation 3.135v v dd 3.465v 1 mv/ v v cm output resistance | i out | 1ma 2 the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) digital inputs and digital outputs symbol parameter conditions min typ max units encode inputs (enc + , enc C ) v id differential input voltage (note 7) l 0.2 v v icm common mode input voltage internally set externally set (note 7) 1.2 1.6 3 v r in input resistance (see figure 2) 6 k c in input capacitance (note 7) 3 pf logic inputs (dith, pga, shdn, rand) v ih high level input voltage v dd = 3.3v l 2v v il low level input voltage v dd = 3.3v l 0.8 v i in digital input current v in = 0v to v dd l 10 a c in digital input capacitance (note 7) 1.5 pf logic outputs (cmos mode) ov dd = 3.3v v oh high level output voltage v dd = 3.3v i o = C10a i o = C200a l 3.1 3.299 3.29 v v v ol low level output voltage v dd = 3.3v i o = 160a i o = 1.60ma l 0.01 0.1 0.4 v v i source output source current v out = 0v C50 ma i sink output sink current v out = 3.3v 50 ma ov dd = 2.5v v oh high level output voltage v dd = 3.3v i o = C200a 2.49 v v ol low level output voltage v dd = 3.3v i o = 1.6ma 0.1 v ov dd = 1.8v v oh high level output voltage v dd = 3.3v i o = C200a 1.79 v v ol low level output voltage v dd = 3.3v i o = 1.6ma 0.1 v logic outputs (lvds mode) standard lvds v dd differential output voltage 100 differential load l 247 350 454 mv v os output common mode voltage 100 differential load l 1.125 1.2 1.375 v low power lvds v dd differential output voltage 100 differential load l 125 175 250 mv v os output common mode voltage 100 differential load l 1.125 1.2 1.375 v
ltc2208-14 6 220814fb the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units f s sampling frequency (note 8) l 1 130 mhz t l enc low time duty cycle stabilizer off (note 7) duty cycle stabilizer on (note 7) l l 3.65 2.6 3.846 3.846 1000 1000 ns ns t h enc high time duty cycle stabilizer off (note 7) duty cycle stabilizer on (note 7) l l 3.65 2.6 3.846 3.846 1000 1000 ns ns t ap sample-and-hold aperture delay C1 ns lvds output mode (standard and low power) t d enc to data delay (note 7) l 1.3 2.5 3.8 ns t c enc to clkout delay (note 7) l 1.3 2.5 3.8 ns t skew data to clkout skew (t c -t d ) (note 7) l C0.6 0 0.6 ns t rise output rise time 0.5 ns t fall output fall time 0.5 ns data latency data latency 7 cycles cmos output mode t d enc to data delay (note 7) l 1.3 2.7 4 ns t c enc to clkout delay (note 7) l 1.3 2.7 4 ns t skew data to clkout skew (t c -t d ) (note 7) l C0.6 0 0.6 ns data latency data latency full rate cmos demuxed 7 7 cycles cycles timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 4) symbol parameter conditions min typ max units v dd analog supply voltage (note 8) l 3.135 3.3 3.465 v p shdn shutdown power shdn = v dd 0.2 mw standard lvds output mode ov dd output supply voltage (note 8) l 3 3.3 3.6 v i vdd analog supply current l 401 470 ma i ovdd output supply voltage l 71 90 ma p dis power dissipation l 1498 1782 mw low power lvds output mode ov dd output supply voltage (note 8) l 3 3.3 3.6 v i vdd analog supply current l 401 470 ma i ovdd output supply voltage l 40 50 ma p dis power dissipation l 1356 1650 mw cmos output mode ov dd output supply voltage (note 8) l 0.5 3.6 v i vdd analog supply current l 401 470 ma p dis power dissipation l 1320 1551 mw power requirements
ltc2208-14 7 220814fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd, with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3.3v, f sample = 130mhz, lvds outputs, differential enc + / enc C = 2v p-p sine wave with 1.6v common mode, input range = 2.25v p-p with differential drive (pga = 0), unless otherwise speci? ed. note 5: integral nonlinearity is de? ned as the deviation of a code from a best ? t straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C 1/2lsb when the output code ? ickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2s complement output mode. note 7: guaranteed by design, not subject to test. note 8: recommended operating conditions. lvds output mode timing all outputs are differential and have lvds levels electrical characteristics timing diagram t h t d t c t l n C 7 n C 6 n C 5 n C 4 n C 3 analog input enc C enc + clkout C clkout + d0-d13, of 220814 td01 t ap n + 1 n + 2 n + 4 n + 3 n
ltc2208-14 8 220814fb demultiplexed cmos output mode timing all outputs are single-ended and have cmos levels full-rate cmos output mode timing all outputs are single-ended and have cmos levels t ap analog input t h t d t c t l n C 7 n C 6 n C 5 n C 4 n C 3 enc C enc + clkouta clkoutb da0-da13, ofa db0-db13, ofb 220814 td02 high impedance n + 1 n + 2 n + 4 n + 3 n t h t d t d t c t l n C 8 n C 6 n C 4 n C 7 n C 5 n C 3 enc C enc + clkouta clkoutb da0-da13, ofa db0-db13, ofb 220814 td03 t ap analog input n + 1 n + 2 n + 4 n + 3 n timing diagram
ltc2208-14 9 220814fb integral nonlinearity (inl) vs output code differential nonlinearity (dnl) vs output code ac grounded input histogram 32k point fft, f in = 5.21mhz, C1dbfs, pga = 0, rand = on, dither off output code 0 C1.0 inl error (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 4096 8192 220814 g01 C0.6 0.6 0.8 0.2 12288 16384 output code 0 C0.5 dnl error (lsb) C0.4 C0.2 C0.1 0 0.5 0.2 4096 8192 220814 g02 C0.3 0.3 0.4 0.1 12288 16384 output code 8176 count 150000 200000 250000 8184 220814 g03 100000 50000 0 8178 8180 8182 8186 frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g04 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 32k point fft, f in = 15.11mhz, C1dbfs, pga = 0, rand = on, dither off frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g05 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 128k point fft, f in = 15.11mhz, C40dbfs, pga = 0, rand = on, dither off frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g06 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 128k point fft, f in = 15.11mhz, C40dbfs, pga = 0, rand = on, dither on 32k point 2-tone fft, f in = 20.14mhz and 14.25mhz, C7dbfs, pga = 0, rand = on, dither off frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g07 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g08 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 32k point 2-tone fft, f in = 20.14mhz and 14.25mhz, C25dbfs, pga = 0, rand = on, dither off frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g09 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 typical performance characteristics
ltc2208-14 10 220814fb sfdr vs input level, f in = 15.1mhz, pga = 0, rand = on, dither off input level (dbfs) C80 0 sfdr (dbc and dbfs) 20 40 60 80 C60 C40 C20 0 220814 g10 100 120 C70 C50 C30 C10 32k point fft, f in = 30.11mhz, C1dbfs, pga = 0, rand = on, dither off input level (dbfs) C80 0 sfdr (dbc and dbfs) 20 40 60 80 C60 C40 C20 0 220814 g11 100 120 C70 C50 C30 C10 sfdr vs input level, f in = 15.1mhz, pga = 0, rand = on, dither on frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g12 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 32k point fft, f in = 30.11mhz, C25dbfs, pga = 0, rand = on, dither on frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g13 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 32k point fft, f in = 70.11mhz, C1dbfs, pga = 0, rand = on, dither off 32k point fft, f in = 70.11mhz, C10dbfs, pga = 0, rand = on, dither off frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g15 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 128k point fft, f in = 70.11mhz, C40dbfs, pga = 0, rand = on, dither off 128k point fft, f in = 70.11mhz, C40dbfs, pga = 0, rand = on, dither on 32k point fft, f in = 70.11mhz, C1dbfs, pga = 1, rand = on, dither off frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g16 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g17 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g18 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g14 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 typical performance characteristics
ltc2208-14 11 220814fb sfdr vs input level, f in = 70.2mhz, pga = 0, rand = on, dither off sfdr vs input level, f in = 70.2mhz, pga = 0, rand = on, dither on 32k point 2-tone fft, f in = 67.2mhz and 74.4mhz, C15dbfs, pga = 0, rand = on, dither off 32k point fft, f in = 140.11mhz, C1dbfs, pga = 0, rand = on, dither off 32k point fft, f in = 140.11mhz, C1dbfs, pga = 1, rand = on, dither off 32k point fft, f in = 170.1mhz, C1dbfs, pga = 1, rand = on, dither off input level (dbfs) C80 0 sfdr (dbc and dbfs) 20 40 60 80 C60 C40 C20 0 220814 g19 100 120 C70 C50 C30 C10 input level (dbfs) C80 0 sfdr (dbc and dbfs) 20 40 60 80 C60 C40 C20 0 220814 g20 100 120 C70 C50 C30 C10 32k point 2-tone fft, f in = 67.2mhz and 74.4mhz, C7dbfs, pga = 0, rand = on, dither off frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g21 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g22 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g23 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g24 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 sfdr vs input level, f in = 140.1mhz, pga = 1, rand = on, dither off input level (dbfs) C80 0 sfdr (dbc and dbfs) 20 40 60 80 C60 C40 C20 0 220814 g25 100 120 C70 C50 C30 C10 sfdr vs input level, f in = 140.1mhz, pga = 1, rand = on, dither on input level (dbfs) C80 0 sfdr (dbc and dbfs) 20 40 60 80 C60 C40 C20 0 220814 g26 100 120 C70 C50 C30 C10 frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g27 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 typical performance characteristics
ltc2208-14 12 220814fb 32k point fft, f in = 250.11mhz, C10dbfs, pga = 1, rand = on, dither off 32k point fft, f in = 380.11mhz, C1dbfs, pga = 1, rand = on, dither off 32k point fft, f in = 380.11mhz, C10dbfs, pga = 1, rand = on, dither off frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g29 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g30 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g31 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 sfdr (hd2 and hd3) vs input frequency snr vs input frequency snr and sfdr vs sample rate f in = 5.1mhz, C1dbfs snr and sfdr vs supply voltage (v dd ), f in = 5.1mhz, C1dbfs i vdd vs sample rate, f in = 5.1mhz, C1dbfs sample rate (msps) 0 350 i vdd (ma) 370 390 410 430 40 80 120 160 220814 g36 450 470 20 60 100 140 v dd = 3.47v v dd = 3.13v v dd = 3.3v 32k point fft, f in = 250.11mhz, C1dbfs, pga = 1, rand = on, dither off frequency (mhz) 0 amplitude (dbfs) C80 C20 C10 0 20 40 50 220814 g28 C100 C110 C40 C60 C90 C30 C120 C50 C70 10 30 60 input frequency (mhz) 0 65 sfdr (dbc) 70 80 85 90 200 110 220814 g32 75 100 50 250 150 300 95 100 105 pga = 1 pga = 0 input frequency (mhz) 0 78 77 76 75 74 73 72 71 220814 g33 100 pga = 0 200 300 snr (dbfs) pga = 1 sample rate (msps) 0 snr and sfdr (dbfs) 90 100 200 220814 g34 80 70 50 100 150 25 75 125 175 110 85 95 75 105 sfdr snr supply voltage (v) 2.8 snr and sfdr (dbfs) 90 95 100 3.6 220814 g35 85 80 70 3.0 3.2 sfdr snr 3.4 75 110 105 typical performance characteristics
ltc2208-14 13 220814fb snr and sfdr vs duty cycle duty cycle (%) 30 sfdr and snr (dbfs) 80 90 70 220814 g37 70 60 40 50 60 110 100 sfdr dcs on sfdr dcs off snr dcs off snr dcs on gain error drift vs temperature, internal reference, drift from 25c temperature (c) C50 C0.1 0 0.2 10 50 220814 g38 C0.2 C0.3 C30 C10 30 70 90 C0.4 C0.5 0.1 gain error drift (%) gain error drift vs temperature, external reference, drift from 25c temperature (c) C50 C0.12 gain error drift (%) C0.10 C0.06 C0.04 C0.02 0.08 0.02 C10 30 50 220814 g39 C0.08 0.04 0.06 0 C30 10 70 90 input offset voltage drift vs temperature, drift from 25c snr and sfdr vs input common mode voltage temperature (c) C50 input offset voltage (mv) 0.15 0.20 0.24 10 50 220814 g40 0.10 0.05 C30 C10 30 70 90 0 C0.05 input common mode voltage (v) 0.50 60 snr (dbfs) and sfdr (dbc) 70 80 90 100 0.75 1.00 1.25 sfdr snr 1.50 220814 g41 1.75 2.00 typical performance characteristics mid-scale settling after wake up from shutdown or starting encode clock time after wake-up or clock start (s) 0 full-scale error (%) 0.2 0.6 1.0 400 2208 g42 C0.2 C0.6 0 0.4 0.8 C0.4 C0.8 C1.0 100 50 200 150 300 350 450 250 500 time from wake-up or clock start (s) 0 full-scale error (%) 1 3 5 800 2208 g43 C1 C3 0 2 4 C2 C4 C5 200 100 400 300 600 700 900 500 1000 full-scale settling after wake up from shutdown or starting encode clock
ltc2208-14 14 220814fb for cmos mode. full rate or demultiplexed sense (pin 1): reference mode select and external reference input. tie sense to v dd to select the internal 2.5v bandgap reference. an external reference of 2.5v or 1.25v may be used; both reference values will set a full scale adc range of 2.25v (pga = 0). gnd (pins 2, 4, 7, 10, 11, 14, 18): adc power ground. v cm (pin 3): 1.25v output. optimum voltage for input com- mon mode. must be bypassed to ground with a minimum of 2.2f. ceramic chip capacitors are recommended. v dd (pins 5, 6, 15, 16, 17): 3.3v analog supply pin. bypass to gnd with 0.1f ceramic chip capacitors. a in + (pin 8): positive differential analog input. a in C (pin 9): negative differential analog input. enc + (pin 12): positive differential encode input. the sampled analog input is held on the rising edge of enc + . internally biased to 1.6v through a 6.2k resistor. output data can be latched on the rising edge of enc + . enc C (pin 13): negative differential encode input. the sampled analog input is held on the falling edge of enc C . internally biased to 1.6v through a 6.2k resistor. by- pass to ground with a 0.1f capacitor for a single-ended encode signal. shdn (pin 19): power shutdown pin. shdn = low results in normal operation. shdn = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. dith (pin 20): internal dither enable pin. dith = low disables internal dither. dith = high enables internal dither. refer to internal dither section of this data sheet for details on dither operation. nc (pins 21, 22): no connect. db0-db13 (pins 23-30 and 33-38): digital outputs, b bus. db13 is the msb. active in demultiplexed mode. the b bus is in high impedance state in full rate cmos mode. ognd (pins 31 and 50): output driver ground. ov dd (pins 32 and 49): positive supply for the output drivers. bypass to ground with o.1f capacitor. ofb (pin 39): over? ow/under? ow digital output for the b bus. ofb is high when an over or under ? ow has occurred on the b bus. this pin goes to high impedance state in full rate cmos mode. clkoutb (pin 40): data valid output. clkoutb will toggle at the sample rate in full rate cmos mode or at 1/2 the sample rate in demultiplexed mode. latch the data on the falling edge of clkoutb. clkouta (pin 41): inverted data valid output. clkouta will toggle at the sample rate in full rate cmos mode or at 1/2 the sample rate in demultiplexed mode. latch the data on the rising edge of clkouta. dnc (pins 42, 43): do not connect in cmos mode. da0-da13 (pins 44-48 and 51-59): digital outputs, a bus. da13 is the msb. output bus for full rate cmos mode and demultiplexed mode. ofa (pin 60): over? ow/under? ow digital output for the a bus. ofa is high when an over or under ? ow has oc- curred on the a bus. lvds (pin 61): data output mode select pin. connecting lvds to 0v selects full rate cmos mode. connecting lvds to 1/3v dd selects demultiplexed cmos mode. connecting lvds to 2/3v dd selects low power lvds mode. connect- ing lvds to v dd selects standard lvds mode. mode (pin 62): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and disables the clock duty cycle stabilizer. connecting mode to 1/3v dd selects offset binary output format and enables the clock duty cycle sta- bilizer. connecting mode to 2/3v dd selects 2s complement output format and enables the clock duty cycle stabilizer. connecting mode to v dd selects 2s complement output format and disables the clock duty cycle stabilizer. rand (pin 63): digital output randomization selection pin. rand low results in normal operation. rand high selects d1-d13 to be exclusive-ored with d0 (the lsb). the output can be decoded by again applying an xor operation between the lsb and all other bits. this mode of operation reduces the effects of digital output interference. pin functions
ltc2208-14 15 220814fb pga (pin 64): programmable gain ampli? er control pin. low selects a front-end gain of 1, input range of 2.25v p-p . high selects a front-end gain of 1.5, input range of 1.5v p-p . gnd (exposed pad): adc power ground. the exposed pad on the bottom of the package must be soldered to ground. for lvds mode. standard or low power sense (pin 1): reference mode select and external reference input. tie sense to v dd to select the internal 2.5v bandgap reference. an external reference of 2.5v or 1.25v may be used; both reference values will set a full scale adc range of 2.25v (pga = 0). gnd (pins 2, 4, 7, 10, 11, 14, 18): adc power ground. v cm (pin 3): 1.25v output. optimum voltage for input com- mon mode. must be bypassed to ground with a minimum of 2.2f. ceramic chip capacitors are recommended. v dd (pins 5, 6, 15, 16, 17): 3.3v analog supply pin. bypass to gnd with 0.1f ceramic chip capacitors. a in + (pin 8): positive differential analog input. a in C (pin 9): negative differential analog input. enc + (pin 12): positive differential encode input. the sampled analog input is held on the rising edge of enc + . internally biased to 1.6v through a 6.2k resistor. output data can be latched on the rising edge of enc + . enc C (pin 13): negative differential encode input. the sampled analog input is held on the falling edge of enc C . internally biased to 1.6v through a 6.2k resistor. by- pass to ground with a 0.1f capacitor for a single-ended encode signal. shdn (pin 19): power shutdown pin. shdn = low results in normal operation. shdn = high results in powered down analog circuitry and the digital outputs are set in high impedance state. dith (pin 20): internal dither enable pin. dith = low disables internal dither. dith = high enables internal dither. refer to internal dither section of the data sheet for details on dither operation. nc (pins 21, 22): no connect. nc (pins 23, 24): do not connect in lvds mode. d0 C /d0 + to d13 C /d13 + (pins 25-30, 33-38, 41-48 and 51-58): lvds digital outputs. all lvds outputs require differential 100 termination resistors at the lvds receiver. d13 + /d13 C is the msb. ognd (pins 31 and 50): output driver ground. ov dd (pins 32 and 49): positive supply for the output drivers. bypass to ground with 0.1f capacitor. clkout C /clkout + (pins 39 and 40): lvds data valid 0utput. latch data on the rising edge of clkout + , falling edge of clkout C . of C /of + (pins 59 and 60): over? ow/under? ow digital out- put of is high when an over or under ? ow has occurred. lvds (pin 61): data output mode select pin. connecting lvds to 0v selects full rate cmos mode. connecting lvds to 1/3v dd selects demultiplexed cmos mode. connecting lvds to 2/3v dd selects low power lvds mode. connect- ing lvds to v dd selects standard lvds mode. mode (pin 62): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and disables the clock duty cycle stabilizer. connecting mode to 1/3v dd selects offset binary output format and enables the clock duty cycle sta- bilizer. connecting mode to 2/3v dd selects 2s complement output format and enables the clock duty cycle stabilizer. connecting mode to v dd selects 2s complement output format and disables the clock duty cycle stabilizer. rand (pin 63): digital output randomization selection pin. rand low results in normal operation. rand high selects d1-d13 to be exclusive-ored with d0 (the lsb). the output can be decoded by again applying an xor operation between the lsb and all other bits. the mode of operation reduces the effects of digital output interference. pga (pin 64): programmable gain ampli? er control pin. low selects a front-end gain of 1, input range of 2.25v p-p . high selects a front-end gain of 1.5, input range of 1.5v p-p . gnd (exposed pad pin 65): adc power ground. the exposed pad on the bottom of the package must be sol- dered to ground. pin functions
ltc2208-14 16 220814fb figure 1. functional block diagram adc clocks differential input low jitter clock driver dither signal generator first pipelined adc stage fifth pipelined adc stage fourth pipelined adc stage second pipelined adc stage enc + enc C correction logic and shift register dith m0de ognd clkout+ clkoutC of + of C d13 + d13 C ov dd d0 + d0 C 220814 f01 input s/h a in C a in + third pipelined adc stage output drivers control logic pga rand lvds shdn ? ? ? v dd gnd pga sense v cm buffer adc reference voltage reference range select block diagram
ltc2208-14 17 220814fb if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 3rd order imd terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). the 3rd order imd is de? ned as the ratio of the rms value of either input tone to the rms value of the largest 3rd order imd product. spurious free dynamic range (sfdr) the ratio of the rms input signal amplitude to the rms value of the peak spurious spectral component expressed in dbc. sfdr may also be calculated relative to full scale and expressed in dbfs. full power bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when a rising enc + equals the enc C voltage to the instant that the input signal is held by the sample- and-hold circuit. aperture delay jitter the variation in the aperture delay time from convertion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C 20log (2 ? f in ? t jitter ) operation dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n+d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band lim- ited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components, except the ? rst ? ve harmonics. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = C20log ( (v 2 2 + v 3 2 + v 4 2 + ... v n 2 )/v 1 ) where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.
ltc2208-14 18 220814fb converter operation the ltc2208-14 is a cmos pipelined multistep converter with a front-end pga. as shown in figure 1, the converter has ? ve pipelined adc stages; a sampled analog input will result in a digitized value seven cycles later (see the timing diagram). the analog input is differential for im- proved common mode noise immunity and to maximize the input range. additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. the encode input is also differential for improved common mode noise immunity. the ltc2208-14 has two phases of operation, determined by the state of the differential enc + /enc C input pins. for brevity, the text will refer to enc + greater than enc C as enc high and enc + less than enc C as enc low. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage ampli? er. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is ampli? ed and output by the residue ampli? er. successive stages oper- ate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when enc is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that enc transitions from low to high, the voltage on the sample capacitors is held. while enc is high, the held input voltage is buffered by the s/h ampli? er which drives the ? rst pipelined adc stage. the ? rst stage acquires the output of the s/h ampli? er during the high phase of enc. when enc goes back low, the ? rst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when enc goes high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the ? fth stage for ? nal evaluation. each adc stage following the ? rst has additional range to accommodate ? ash and ampli? er offset errors. results from all of the adc stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2208-14 cmos differential sample and hold. the differential ana- log inputs are sampled directly onto sampling capacitors (c sample ) through nmos transitors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when enc is low, the nmos transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. when enc transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when enc is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as enc transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the figure 2. equivalent input circuit c sample 4.9pf r parasitic 3 r parasitic 3 r on 20 r on 20 v dd ltc2208-14 a in + a in C 220814 f02 c sample 4.9pf v dd v dd enc C enc + 1.6v 6k 1.6v 6k c parasitic 1.8pf c parasitic 1.8pf applications information
ltc2208-14 19 220814fb input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. common mode bias the adc sample-and-hold circuit requires differential drive to achieve speci? ed performance. each input should swing 0.5625v for the 2.25v range (pga = 0) or 0.375v for the 1.5v range (pga = 1), around a common mode voltage of 1.25v. the v cm output pin (pin 3) is designed to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with 2.2f or greater. input drive impedance as with all high performance, high speed adcs the dy- namic performance of the ltc2208-14 can be in? uenced by the input drive circuitry, particularly the second and third harmonics. source impedance and input reactance can in? uence sfdr. at the falling edge of enc the sample and hold circuit will connect the 4.9pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when enc rises, holding the sampled input on the sampling capacitor. ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance it is recommended to have a source impedance of 100 or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits input filtering a ? rst order rc low pass ? lter at the input of the adc can serve two functions: limit the noise from input circuitry and provide isolation from adc s/h switching. the ltc2208-14 has a very broadband s/h circuit, dc to 700mhz; it can be used in a wide range of applications; therefore, it is not possible to provide a single recommended rc ? lter. figures 3, 4a and 4b show three examples of input rc ? ltering at three ranges of input frequencies. in general it is desirable to make the capacitors as large as can be toleratedthis will help suppress random noise as well as noise coupled from the digital circuitry. the ltc2208- 14 does not require any input ? lter to achieve data sheet speci? cations; however, no ? ltering will put more stringent noise requirements on the input drive circuitry. transformer coupled circuits figure 3 shows the ltc2208-14 being driven by an rf transformer with a center-tapped secondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the adc. source impedance greater than 50 can reduce the input bandwidth and increase high frequency distor- tion. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies below 1mhz. center-tapped transformers provide a convenient means of dc biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. figure 3. single-ended to differential conversion using a transformer. recommended for input frequencies from 5mhz to 100mhz 35 5 35 10 10 5 5 0.1f a in + a in C 8.2pf 2.2f 8.2pf 8.2pf v cm t1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size except 2.2f 220814 f03 ltc2208-14 applications information
ltc2208-14 20 220814fb figure 4a shows transformer coupling using a transmis- sion line balun transformer. this type of transformer has much better high frequency response and balance than ? ux coupled center tap transformers. coupling capaci- tors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25v. figure 4b shows the same circuit with components suit- able for higher input frequencies. figure 5. dc coupled input with differential ampli? er figure 4a. using a transmission line balun transformer. recommended for input frequencies from 100mhz to 250mhz figure 4b. using a transmission line balun transformer. recommended for input frequencies from 250mhz to 500mhz reference operation figure 6 shows the ltc2208-14 reference circuitry con- sisting of a 2.5v bandgap reference, a programmable gain ampli? er and control circuit. the ltc2208-14 has three modes of reference operation: internal reference, 1.25v external reference or 2.5v external reference. to use the internal reference, tie the sense pin to v dd . to use an external reference, simply apply either a 1.25v or 2.5v reference voltage to the sense input pin. both 1.25v and 2.5v applied to sense will result in a full scale range of 2.25v p-p (pga = 0). a 1.25v output, v cm is provided for a common mode bias for input drive circuitry. an external bypass capacitor is required for the v cm output. this provides a high frequency low impedance path to ground for internal and external circuitry. this is also the compensation capacitor for the reference; it will not be stable without this capacitor. the minimum value required for stability is 2.2f. figure 6. reference circuit direct coupled circuits figure 5 demonstrates the use of a differential ampli? er to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop ampli? er will de- grade the adc sfdr at high input frequencies. additionally, wideband op amps or differential ampli? ers tend to have high noise. as a result, the snr will be degraded unless the noise bandwidth is limited prior to the adc input. 0.1f a in + a in C 4.7pf 2.2f 4.7pf 4.7pf v cm ltc2208-14 analog input 0.1f 0.1f 5 10 10 25 25 5 t1 1:1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size except 2.2f 220814 f04a 0.1f 5 25 25 5 a in + a in C 2.2f 2.2pf 2.2pf v cm ltc2208-14 analog input 0.1f 0.1f t1 1:1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size except 2.2f 220814 f04b C C + + a in + a in C 2.2f 12pf 12pf 25 25 v cm ltc2208-14 analog input 220814 f05 cm amplifier = ltc6600-20, lt1993, etc. high speed differential amplifier pga 1.25v sense v cm buffer internal adc reference range select and gain control 2.5v bandgap reference 2.2 f tie to v dd to use internal 2.5v reference or input for external 2.5v reference or input for external 1.25v reference 220814 f06 applications information
ltc2208-14 21 220814fb the internal programmable gain ampli? er provides the internal reference voltage for the adc. this ampli? er has very stringent settling requirements and is not accessible for external use. the sense pin can be driven 5% around the nominal 2.5v or 1.25v external reference inputs. this adjustment range can be used to trim the adc gain error or other system gain errors. when selecting the internal reference, the sense pin should be tied to v dd as close to the converter as possible. if the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1f ceramic capacitor. figure 7. a 2.25v range adc with an external 2.5v reference in applications where jitter is critical (high input frequen- cies), take the following into consideration: 1. differential drive should be used. 2. use as large an amplitude possible. if using trans- former coupling, use a higher turns ratio to increase the amplitude. 3. if the adc is clocked with a ? xed frequency sinusoidal signal, ? lter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.2v to 3v. each input may be driven from ground to v dd for single-ended drive. pga pin the pga pin selects between two gain settings for the adc front-end. pga = 0 selects an input range of 2.25v p-p ; pga = 1 selects an input range of 1.5v p-p . the 2.25v input range has the best snr; however, the distortion will be higher for input frequencies above 100mhz. for applica- tions with high input frequencies, the low input range will have improved distortion; however, the snr will be approximately 1.8db worse. see the typical performance characteristics section. driving the encode inputs the noise performance of the ltc2208-14 can depend on the encode signal quality as much as on the analog input. the encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 6k resistor to a 1.6v bias. the bias resistors set the dc operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. any noise present on the encode signal will result in ad- ditional aperture jitter that will be rms summed with the inherent adc aperture jitter. figure 8a. equivalent encode input circuit figure 8b. transformer driven encode v cm sense 1.25v 3.3v 2.2f 2.2f 1f 220814 f07 ltc2208-14 lt1461-2.5 2 6 4 v dd v dd ltc2208-14 220814 f08a v dd enc C enc + 1.6v 1.6v 6k 6k to internal adc clock drivers 50 100 8.2pf 0.1f 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 ltc2208-14 220814 f08b enc C enc + applications information
ltc2208-14 22 220814fb the lower limit of the ltc2208-14 sample rate is determined by droop of the sample and hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the speci? ed minimum operating frequency for the ltc2208-14 is 1msps. digital outputs digital output modes the ltc2208-14 can operate in four digital output modes: standard lvds, low power lvds, full rate cmos, and demultiplexed cmos. the lvds pin selects the mode of operation. this pin has a four level logic input, centered at 0, 1/3v dd , 2/3v dd and v dd . an external resistor divider can be used to set the 1/3v dd and 2/3v dd logic levels. table 1 shows the logic states for the lvds pin. table 1. lvds pin function lvds digital output mode 0v(gnd) full-rate cmos 1/3v dd demultiplexed cmos 2/3v dd low power lvds v dd lv d s digital output buffers (cmos modes) figure 11 shows an equivalent circuit for a single output buffer in cmos mode, full-rate or demultiplexed. each buffer is powered by ov dd and ognd, isolated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 to external circuitry and eliminates the need for external damping resistors. as with all high speed/high resolution converters, the digital output loading can affect the performance. the digital outputs of the ltc2208-14 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as a alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. a resistor in series with the figure 10. enc drive using a cmos to pecl translator maximum and minimum encode rates the maximum encode rate for the ltc2208-14 is 130msps. for the adc to operate properly the encode signal should have a 50% (5%) duty cycle. each half cycle must have at least 3.65ns for the adc internal circuitry to have enough settling time for proper operation. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. when using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. an optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. this circuit uses the rising edge of enc pin to sample the analog input. the falling edge of enc is ignored and an internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin must be connected to 1/3v dd or 2/3v dd using external resistors. figure 9. single-ended enc drive, not recommended for low jitter 220814 f09 enc C 1.6v v threshold = 1.6v enc + 0.1f ltc2208-14 220814 f10 enc C enc + 3.3v 3.3v d0 q0 q0 mc100lvelt22 ltc2208-14 83 83 130 130 applications information
ltc2208-14 23 220814fb resistor, even if the signal is not used (such as of + /of C or clkout + /clkout C ). to minimize noise the pc board traces for each lvds output pair should be routed close together. to minimize clock skew, all lvds pc board traces should have about the same length. in low power lvds mode 1.75ma is steered between the differential outputs, resulting in 175mv at the lvds receivers 100 termination resistor. the output com- mon mode voltage is 1.20v, the same as standard lvds mode. data format the ltc2208-14 parallel digital output can be selected for offset binary or 2s complement format. the format is selected with the mode pin. this pin has a four level logic input, centered at 0, 1/3v dd , 2/3v dd and v dd . an external resistor divider can be used to set the 1/3v dd and 2/3v dd logic levels. table 2 shows the logic states for the mode pin. table 2. mode pin function mode output format clock duty cycle stabilizer 0(gnd) offset binary off 1/3v dd offset binary on 2/3v dd 2s complement on v dd 2s complement off figure 11. equivalent circuit for a digital output buffer output may be used but is not required since the adc has a series resistor of 43 on-chip. lower ov dd voltages will also help reduce interference from the digital outputs. digital output buffers (lvds modes) figure 12 shows an equivalent circuit for an lvds output pair. a 3.5ma current is steered from out + to out C or vice versa, which creates a 350mv differential voltage across the 100 termination resistor at the lvds receiver. a feedback loop regulates the common mode output volt- age to 1.20v. for proper operation each lvds output pair must be terminated with an external 100 termination figure 12. equivalent output buffer in lvds mode ltc2208-14 220814 f11 ov dd v dd v dd 0.1 f typical data output ognd 43 ov dd 0.5v to 3.6v predriver logic data from latch ltc2208-14 220814 f12 3.5ma 1.20v lvds receiver ognd 10k 10k v dd v dd 0.1 f ov dd 3.3v predriver logic data from latch + C ov dd ov dd 43 43 100 applications information
ltc2208-14 24 220814fb over? ow bit an over? ow output bit (of) indicates when the converter is overranged or underranged. in cmos mode, a logic high on the ofa pin indicates an over? ow or under? ow on the a data bus, while a logic high on the ofb pin indicates an over? ow on the b data bus. in lvds mode, a differen- tial logic high on of + /of C pins indicates an over? ow or under? ow. output clock the adc has a delayed version of the encode input avail- able as a digital output, clkout. the clkout pin can be used to synchronize the converter data to the digital system. this is necessary when using a sinusoidal en- code. in both cmos modes, a bus data will be updated as clkouta falls and clkoutb rises. in demultiplexed cmos mode the b bus data will be updated as clkouta falls and clkoutb rises. in full rate cmos mode, only the a data bus is active; data may be latched on the rising edge of clkouta or the falling edge of clkoutb. in demultiplexed cmos mode clkouta and clkoutb will toggle at 1/2 the frequency of the encode signal. both the a bus and the b bus may be latched on the rising edge of clkouta or the falling edge of clkoutb. digital output randomizer interference from the adc digital outputs is sometimes unavoidable. interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can result in discernible unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise ? oor for a large reduction in unwanted tone amplitude. the digital output is randomized by applying an exclu- sive-or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied; that is, an exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout outputs are not affected. the output randomizer function is active when the rand pin is high. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example, if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. in cmos mode ov dd can be powered with any logic voltage up to the 3.6v. ognd can be powered with any voltage from ground up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . in lvds mode, ov dd should be connected to a 3.3v supply and ognd should be connected to gnd. figure 13. functional equivalent of digital output randomizer ? ? ? clkout of d13/d0 d12/d0 d2/d0 d1/d0 d0 d0 d1 rand = high, randomizer enabled d2 d12 d13 of clkout rand 220814 f13 applications information
ltc2208-14 25 220814fb figure 14. derandomizing a randomized digital output internal dither the ltc2208-14 is a 14-bit adc with a very linear transfer function; however, at low input levels even slight imperfec- tions in the transfer function will result in unwanted tones. small errors in the transfer function are usually a result of adc element mismatches. an optional internal dither mode can be enabled to randomize the input location on the adc transfer curve, resulting in improved sfdr for low signal levels. as shown in figure 15, the output of the sample-and-hold ampli? er is summed with the output of a dither dac. the dither dac is driven by a long sequence pseudo-random number generator; the random number fed to the dither dac is also subtracted from the adc result. if the dither dac is precisely calibrated to the adc, very little of the dither signal will be seen at the output. the dither signal that does leak through will appear as white noise. the dither dac is calibrated to result in less than 0.5db elevation in the noise ? oor of the adc, as compared to the noise ? oor with dither off. figure 15. functional equivalent block diagram of internal dither circuit ? ? ? d1 d0 d2 d12 d13 ltc2208-14 pc board fpga clkout of d13/d0 d12/d0 d2/d0 d1/d0 d0 220814 f14 +C ain C ain + s/h amp digital summation output drivers multibit deep pseudo-random number generator 14-bit pipelined adc core precision dac clock/duty cycle control clkout of d13 ? ? ? d0 enc dither enable high = dither on low = dither off dith enc analog input 220814 f15 ltc2208-14 applications information
ltc2208-14 26 220814fb grounding and bypassing the ltc2208-14 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the ltc2208-14 has been optimized for a ? owthrough layout so that the interaction between inputs and digital outputs is minimized. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd, v cm , and ov dd pins. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc2208-14 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2208-14 is trans- ferred from the die through the bottom-side exposed pad. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. it is critical that the exposed pad and all ground pins are connected to a ground plane of suf? cient area with as many vias as possible. applications information
ltc2208-14 27 220814fb up package 64-lead plastic qfn (9mm 9mm) (reference ltc dwg # 05-08-1705 rev c) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description 9 .00 p 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation wnjr-5 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale pin 1 top mark (see note 5) 0.40 p 0.10 64 63 1 2 bottom viewexposed pad 7.15 p 0.10 7.15 p 0.10 7.50 ref (4-sides) 0.75 p 0.05 r = 0.10 typ r = 0.115 typ 0.25 p 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (up64) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 p 0.05 7.50 ref (4 sides) 7.15 p 0.05 7.15 p 0.05 8.10 p 0.05 9.50 p 0.05 0.25 p 0.05 0.50 bsc package outline pin 1 chamfer c = 0.35
ltc2208-14 28 220814fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0909 rev b ? printed in usa part number description comments ltc1747 12-bit, 80msps adc 72db snr, 87db sfdr, 48-pin tssop package ltc1748 14-bit, 80msps adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1749 12-bit, 80msps wideband adc up to 500mhz if undersampling, 87db sfdr ltc1750 14-bit, 80msps wideband adc up to 500mhz if undersampling, 90db sfdr lt1993-2 high speed differential op amp 800mhz bw, 70dbc distortion at 70mhz, 6db gain ltc2202 16-bit, 10msps adc 140mw, 81.6db snr, 100db sfdr ltc2203 16-bit, 25msps adc 220mw, 81.6db snr, 100db sfdr ltc2204 16-bit, 40msps adc 480mw, 79.1db snr, 100db sfdr ltc2205 16-bit, 65msps adc 610mw, 79db snr, 100db sfdr ltc2206 16-bit, 80msps adc 725mw, 77.9db snr, 100db sfdr ltc2207 16-bit, 105msps adc 900mw, 77.9db snr, 100db sfdr ltc2208 16-bit, 130msps adc 1250mw, 77.7db snr, 100db sfdr ltc2220 12-bit, 170msps adc 890mw, 67.5db snr, 9mm 9mm qfn package ltc2220-1 12-bit, 185msps adc 910mw, 67.5db snr, 9mm 9mm qfn package ltc2249 14-bit, 65msps adc 230mw, 73db snr, 5mm 5mm qfn package ltc2250 10-bit, 105msps adc 320mw, 61.6db snr, 5mm 5mm qfn package ltc2251 10-bit, 125msps adc 395mw, 61.6db snr, 5mm 5mm qfn package ltc2252 12-bit, 105msps adc 320mw, 70.2db snr, 5mm 5mm qfn package ltc2253 12-bit, 125msps adc 395mw, 70.2db snr, 5mm 5mm qfn package ltc2254 14-bit, 105msps adc 320mw, 72.5db snr, 5mm 5mm qfn package ltc2255 14-bit, 125msps adc 395mw, 72.4db snr, 5mm 5mm qfn package ltc2299 dual 14-bit, 80msps adc 445mw, 73db snr, 9mm 9mm qfn package lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if ampli? er/adc driver with digitally controlled gain 450mhz 1db bw, 47db oip3, digital gain control 10.5db to 33db in 1.5db/step lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 50 single-ended rf and lo ports related parts

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